Title:
F4kEOUT: Leveraging Cache Contention for Cross-Thread Data Leakage
Poster
Preview Converted Images may contain errors
Abstract
Microarchitectural side channel attacks pose significant threats to the security of modern computer systems. In this research, I introduce a novel side channel attack that leverages 4k aliasing and cache contention. My proposed attack capitalizes on the inherent behavior of modern processors, exploiting the shared cache architecture and microarchitecture optimizations to extract data across security boundaries. Through extensive experimentation and analysis, I demonstrate the effectiveness of the attack methodology. My findings highlight the importance of addressing microarchitectural vulnerabilities and the need for robust defense mechanisms to safeguard against emerging threats. This research contributes to the broader understanding of microarchitectural security and provides valuable insights for designing secure computing systems.
Authors
First Name |
Last Name |
Skylar
|
Gagnon
|
Leave a comment
Submission Details
Conference URC
Event Interdisciplinary Science and Engineering (ISE)
Department Electrical and Computer Engineering (ISE)
Added April 16, 2024, 1:36 p.m.
Updated April 17, 2024, 11:02 a.m.
See More Department Presentations Here